Implementation and proficiency analysis of enhanced graph algorithm for DC microgrid applications

Integrating renewable energy generation with the conventional grid supports reduces carbon emissions in the atmosphere. Despite technical advancements in protection strategies, critical issues concerning renewable integration in microgrid structures require standardized solutions. The essential aspects that need to be concentrated during securing the grids are rapid fault interruption, false tripping and blinding of protection. This study proposes an innovative approach to enhance fault isolation speed through the implementation of a grid monitoring system (GMS) coupled with a fault identification method based on Kosaraju’s algorithm. This algorithm operates on the principles of overvoltage and overcurrent detection. The study assesses the efficacy of this approach by examining its integration with a Z-source circuit breaker and conducting tests on different fault types within a 13-bus system. Real-time simulations using Opal RT software are employed to experimentally validate the proposed methodology, ensuring its efficacy in fault interruption and isolation.

faults and transients without undue delay.Additionally, Dial's algorithm plays a crucial role in determining the shortest path for a fault to travel from its origin to the nearest DG, enabling the tripping of the breaker closest to the fault location.
As the proposed fault detection technique works bi-directionally, the reverse fault current detection and interruption and the efficacy of the proposed solution will be proven through experimental results obtained using an Opal Real-Time Simulator.The intended outcome of this paper is to analyse all challenges, particularly those related to protecting the DC microgrid using algorithm-based protection for system modelling and data analysis.The paper's organization is as follows: Section II briefly describes the modelling of a nine-bus DC microgrid system and Z-source breaker topologies.Section III explains fault detection using the Kosaraju's algorithm with the overcurrent detection principle.Section IV discusses the proposed work's results.Section V briefs the conclusion and future works.

Modelling of thirteen bus DC microgrid system
An isolated/autonomous microgrid operates exclusively, where each unit in the microgrid connects to a 600 V DC bus.The DC link capacitor controls the DC voltage and keeps it steady at the DC bus.The algorithm based adaptive protection supports protection for LVDC and MVDC system with range upto 5 kV.In this article a 600 V, 30 kW system with renewable resources considered includes a 3kWh battery, a 15 kW Photovoltaic module, and a 12 kW Permanent Magnet Synchronous Generator (PMSG)-based wind turbine.
The integration of a Photovoltaic (PV) array into a DC microgrid enhances real-time system performance.Incorporating PV panels in series increases voltage, while parallel-connected PV panels boost current output.With a solar irradiance level of 1000W/m 2 , the PV module design is grounded on the Shockley diode equation.
Considering V pv = V oc , N p = 1 and N s = 30, the PV module is designed based on the given equation for I PV which can be denoted as, where I ph is the photo-current of a module, I rs is the reverse saturation current of a module, I PV is the output current of a PV module, I o is the saturation current of a module which varies with temperature of a cell, number of cells connected in series is denoted as N s and R s is series resistance respectively.Depending on the voltage and current requirement, the proposed PV array consists of 31 PV modules integrated to extract an output voltage of 600 V for a standard solar irradiance with cell temperature maintained at 1000W/m 2 and 25 °C respectively 28 .Furthermore, the boost converter interfaced with the photo-voltaic array to increase the required voltage levels.
In a PMSG, the permanent magnet in the rotor provides the field excitation.Considering a fixed speed wind turbine with a wind speed taken as 72 m/s and zero pitch angle is 0°, the aerodynamic model of a wind turbine is given by where P is the wind power generated, ρ is air density, A is the area covered by the blades, v is the wind speed, Cp is the power coefficient and λ is tip speed ratio.
The tip speed ratio of a wind turbine is given by (1) where n is wind turbine rotor speed in revolutions per minute(r/min).
The fixed-speed PMSG wind turbine is designed to produce an output of 600 V.The torque generated by the wind turbine is then directed to the PMSM generator, which converts the mechanical energy to 3-phase electrical energy.A rectifier is interfaced to convert the AC input from the turbine to DC output with an LC filter with values of 47 and 220 µF, respectively 29 .
Battery modelling is of adequate importance since the microgrid has a bidirectional power flow.So, bidirectional battery modelling with a buck-boost converter is required to interface with the DC bus 30 .The overall DC system is modelled as one point grounding to analyse the proposed strategy under various operating condition.

Response during steady state operation
The modelling of bidirectional DC circuit breaker is depicted in Fig. 1 and the modes of operation are discussed below 23 .In the active state illustrated in (Fig. 1a, b), the inductances of lines L 1 , L 2 , and L L facilitate the flow of I L load current in steady-state, with negligible drop in voltage across the line inductance.Diodes D 1 and D 4 conduct during this phase, while D 2 and D 3 remain reverse-blocking.Under ideal conditions the voltage across the load will be equal to V S , the capacitor C 2 charges to V S and the capacitor C 1 discharges accordingly.Upon reversing the connections between the source and load, the circuit breaker (CB) operates similarly.However, D 2 and D 3 transition to forward conduction, while D 1 and D 4 assume the reverse-blocking state.
In energy storage protection applications, the power flow differs as the existence of bidirectional mode and the precaution is necessary as there is a momentary drop in load current to zero.Hence thyristor functionality should not be affected during the mode transitions.

Response to load side fault
The fault current follows the indicated red path as illustrated in (Fig. 1c); for a fault occurred at the output.This fault current bifurcates into two components ZCB and C. The former flows in the breaker capacitors, while the latter traverses the load capacitance.Upon fault initiation the Z-Source inductors initially endure abrupt changes in current, thus maintaining their currents at their pre-fault levels denoted by I L .Analysing the current at node depicted in Fig. 1c  www.nature.com/scientificreports/exhibit under-damped resonant responses particularly decoupled when the fault impedance is zero.The opening resonance conditions are contingent upon the steady-state operating point of the circuit.As these circuits enter resonance the voltage V C2 declines while v C1 ascends.Upon V C1 surpassing source voltage the inductor voltages dip below zero and are damped by diodes D5 and D6.This action restricts the thyristor voltage from exceeding the source voltage, thereby reducing the forward-blocking voltage requisite of T 1 to V S .The inductor current reaches the current peak of the LC circuit, thereby dissipating the stored energy in the damping diodes (D 5 & D6).In practical implementation a resistor could be introduced in series with the damping diode as depicted in Fig. 1c, to expedite the dissipation of stored energy.However, the voltage drop across the resistor amplifies the blocking state of the thyristor.During resonance the output diode (D 2 or D 4 ) current amounts to the sum of current flowing in two LC series circuits.Conversely, the current in the input diode (D 1 or D 3 ) corresponds solely to that of one LC series by constituting majorly to the output diode current.Notably the time taken by the diode for reverse recovery has no impact the operation of the CB therefore diodes with losses are deemed appropriate.Moreover, the forward voltage drop across a diode typically remains lower than an equivalent thyristor.

Response to source side faults
The proposed circuit breaker (CB) is equipped to individually handle faults occurring at either of the input of bidirectional current flow.This feature enables swift and independent isolation of faulty lines from the source and load.When the breaker is commutated to be in on-state and a fault occurs across the input a portion of the fault current is drawn from the Z-Source capacitors initially.The behaviour of other passive components varies depending on the load capacitance, as outlined below.

RC load
In scenarios where a short circuit fault emerges with existing load capacitance, the fault current follows the pattern illustrated in Fig. 1d.Initially the fault current comprises If ZCB , i fc , and i fS .Under these conditions the collapsing input voltage triggers the deactivation of D1 and D4 while D3 and D2 activate.The fault current originating from the DC source (i fs ) is constrained to the line inductance I L .
Similarly the fault current (i fc ) sourced from CL is limited to line inductance by the inductors and also the capacitance connected to the Z-Source contributes to the fault current of ZCB.Monitoring the cathode current of T 1 when i 1 equals I L (the current passing through L 2 ), T 1 's current decreases to zero and leading to its commutation off.Subsequently, upon T 1 's deactivation two LC resonant circuits connected in series are established as one involving C 2 , L 2 , and the fault and the other comprising C 1 , C L , L 1 , and the fault.These circuits decouple when the fault impedance becomes zero.
The conditions for resonance are dictated by the steady-state operating point of the circuit, with a response analogous to that described in Subsection 3.2 for an output fault.However, in this scenario the load capacitance influences the reaction of one LC circuit.The proposed circuit breaker (CB) is equipped to autonomously handle faults occurring at its source irrespective of the primary direction of current flow.This feature enables swift and independent isolation of faulty lines from a DC power system.And when the breaker is in operational state and a fault occurs across its source terminals, a portion of the initial fault current is drawn from the Z-Source capacitors.

Resistive load
When a short circuit fault arises with C L = 0 µF the opening fault current consists of if ZCB and if S , here the voltage at both the source and load side collapses immediately.The opening fault current provided by the DC source (i fs ) is capped at I L by the line inductance L L .Consequently, the Z-Source capacitance supplies current to the fault and the load, effectively perceiving the fault current with the load resistance in parallel.Hence, load resistance can be disregarded when the fault manifests as a short circuit.The thyristor current is driven to zero by if ZCB causing its deactivation.After T 1 's deactivation the current in L 1 is damped by D 5 forming a LC resonant circuit in series through C 2 , L 2 , and the fault.However, in this instance a single LC resonant circuit is present.
Figure 2 illustrates the DC microgrid modelling interfaced with PV, PMSG based wind generation, battery and bidirectional DC circuit breaker.This overall modelling is interfaced with real time simulator OP4500 to test and analyze the protection strategy in real time platform.Figure 3a portrays the grid voltage, grid current and grid power of the DC microgrid rated of 600 V, 50A and 30KW modelled for testing the proposed algorithm.The proposed protection strategy involved with the Z-source breaker in the given 13 bus DC microgrid system is proven to be stable for step load variation in the given system.From the Fig. 3b it is evident that the load current varies for a step variation of load resistance in seconds is not treated as fault and it does not affect the performance of the breaker, thus the breaker is able to clearly identify the difference from fault current and a step load variations ideally.

Fault detection using graph algorithms
As illustrated in Fig. 4 the functioning of 13 bus DC microgrid system is handled by Graph Algorithm Based Protection Controller (GABPC).The GABPC continuously examines the line voltage, line current, bus voltage, bus current and power output from different renewables in the DC microgrid system.Following the conventional approach for overcurrent protection, the algorithm identifies the faulted bus if the line voltage, line current, and bus current exceed the fixed threshold limit.The 13 bus DC microgrid system works based on three algorithms, the first and foremost algorithm is bipartite matching.This algorithm finds the existing configuration and works adaptively by varying its configuration based on demands and necessities.The variation in demand leads to change the configuration from ring to radial or radial to ring to support load sharing.The bipartite matching works as joint or disjoint sets in a graph/network.If the configuration is ring it works based on joint sets and if the configuration is radial it works based on disjoint sets.Notably, the relay settings are monitored and fixed by GABPC considering the voltage, current and power values with a minima and maxima limit of ± 12% of the rated values.On continuation to Bipartite matching, the Kosaraju's algorithm can be implemented to protect a DC microgrid system, which monitors and determines the functional and disengaged buses.The Kosaraju's algorithm determines the strongly connected components (SCCs) which are the subset  of the vertices in a directed graph and the functional bus nodes in the case of a microgrid.Firstly by performing a Depth-First Search (DFS) in the microgrid system, the algorithm starts with a random starting point and records the end vertices after a complete search.Before performing a second DFS the algorithm transposes the original graph by reversing the direction of all the edges.Thus the proposed adaptive protection system can identify a reverse fault current.In the second DFS the starting vertices are chosen in a decreasing fashion of the earlier pass and thus the disengaged node is determined from the strongest connected node.If a faulted node is identified in the process, the Dial's algorithm will step on to determine the shortest path from the faulted node to DG.The Dial's algorithm analyses the shortest path from the faulted node to the nearest DG and initiates the corresponding relay to trip the bidirectional DC circuit breaker.Thus the DG connected near the faulted node is secured prior within the shortest period.

Performance of the algorithm to fault response
Step 1: Initially the algorithm monitors bus voltage and current through GABPC.
Step 2: The bipartite and Kosaraju algorithms work simultaneously to analyse the network configuration of functional and inactive buses.They fix the relay threshold by stacking the values.
Step 3: The bipartite matching analyses the configuration initially and determines whether it is a ring or radial configuration.
Step 4: The relay settings are monitored and adjusted by GABPC using bipartite matching, considering the voltage, current, and power values within a minimum and maximum limit of ± 12% of the rated values.
Step 5: If any abnormalities are found in the stored values, the Kosaraju algorithm immediately tests the functionality of the buses.
Step 6: Continuing from the Kosaraju algorithm, in finding the inactive bus, the current location of the fault is identified.
Step 7: Then, GABPC orders the dial's algorithm to find the shortest path from the faulted point to the nearest presence of renewables.
Step 8: The importance of tripping the breaker nearest to the fault and closest to the renewable source is determined and the corresponding breaker is tripped off.
Step 9: Once again, it is tested for reverse fault, and if a reverse fault is found the corresponding breaker is immediately tripped off.

Implementation of thirteen bus DC microgrid in real time simulation
Prior to engaging in real-time Hardware-in-the-Loop (HIL) testing for a specific system, Software-in-the-Loop (SIL) analysis is conducted.SIL offers a significant advantage by not necessitating peripheral devices, thereby securing the consistency of the signal.Within this segment, mutually the controller and the plant undergo testing utilizing a real-time simulator (OP4500) constructed on the RT-Lab platform.www.nature.com/scientificreports/ Based on the real time data's collected from the PV, Wind, battery and synchronizing panel installed in smart grid laboratory, VIT Chennai, the Simulink models are modelled and integrated with RT blocks and are accessible on the host computer.This host computer is linked to the RT simulation target via a Transmission Control Protocol (TCP)/Internet Protocol (IP) communication network, as illustrated in Fig. 5.To analyse the system dynamics, various fault scenarios such as line-to-line and line-to-ground faults are tested to validate the performance of the proposed algorithm.Furthermore, the impact of different fault types is also evaluated.Realtime data from the panels are transmitted to the Opal RT processor to facilitate precise real-time analysis.And in Fig. 5 the connectivity between the Opal RT simulator and the host PC is illustrated.

Results and discussion
The results are verified in a 13 bus DC microgrid system built in MATLAB Simulink platform integrated with Opal real time (RT) simulator, and the GABPC is interfaced using python program.The proposed graph algorithm based protection strategy is tested and verified in Opal-RT Software in loop (SIL) testing which acts as a real time plant using FPGA processor, and the efficiency of the algorithm is analysed for various operating conditions.. The voltage and current profile of each scenarios is visualized in Digital storage oscilloscope (DSO).During normal and abnormal operating conditions, the bipartite algorithm noted all the parameters and stores in a heap.If the heaped values found abnormal, immediately the information on configuration and signals regarding the abnormal information is sent to kosaraju algorithm by GABPC to find status of active and inactive buses.Furthermore, the signal to find the minimal distance from the current inactive bus to the nearest renewable is investigated by Dial's algorithm through GABPC.Thus, the shortest path and precise fault location is identified and the corresponding circuit breaker is tripped.This action interrupts the fault and additionally checks for reverse faults.The system ensures fault interruption and verification for reverse fault conditions.Figure 6, shows the various fault tested in the 13 bus DC microgrid system.

Evaluation of the proposed system under line-to-line fault
A line-to-line fault (F L ) is simulated to test the real-time performance of the system, where a fault is applied at line L 10-11 for a period of 5 s.The proposed GABPC acts promptly by matching the parameters of the functional nodes in the system using bipartite algorithm, and locates the disengaged nodes using the kosaraju's algorithm in the system.And by analysing the shortest path and their closeness to the DG source, the relay tripping signals are initiated.Thus the GABPC interrupts the fault by initiating the corresponding breakers near the faulted line using relay coordination.Figures 7-9 show that the algorithm's implementation proved its efficacy in fault interruption.
The fault occurred on line L 10-11 and made an impact on the adjacent lines connected to the bus 10 and 11.The difference in voltage and current at the instant of fault is measured by the relays R 11 , R 12 , R 13 and R 19 connected adjacent to the fault locations using bipartite algorithm.The impact of the fault is recoiled with the initializing of a tripping signal of CB 12 by the relay R 12 located in L 10-11 , as described in Fig. 6.
Figure 8 shows that the proposed adaptive protection system can be evaluated from the operation of CB 12 .For the compatibility of the proposed system in OpalRT, the system voltage range 600 V is made delineate to 12 V considering the gain of 50, and the current rating is maintained at 50A.The breaker CB 12 interrupts the line-line fault applied for a period of 5 s where the existing grid voltage and load current were 580 V and 48A respectively.The voltage interruption time (V IT ) and fault current interruption time (C IT ) of breaker are noted as 6.186 ms 6.398 ms correspondingly.After the fault clearing time of 5 s, the breaker CB 12 starts to reclose.The breaker CB 12 recloses with a voltage reclosing time (V RT ) of 39.85 ms and current reclosing time (C RT ) of 35.77 ms as mentioned in Table 2.In Fig. 10, the grid voltage of 620 V and load current of 52A is observed on breaker CB9.Upon the occurrence of a Line-to-Ground fault F G on line L 8-9 , CB 9 trips with an interruption time of V IT 6.614 ms and C IT 6.655 ms from the moment of fault inception.Following fault clearance, CB 9 recloses with a reclosing time (V RT ) of 30.23 ms and a reclosing current time (C RT ) of 49.87 ms.Concurrently, at the moment of fault occurrence on L 8-9 , load 4 connected to bus 9 is susceptible to the fault.Similarly, breaker CB 18 , positioned between bus 9 and load 4, reacts by interrupting the fault.CB 18 's fault interruption occurs at a difference in time from CB 9 's interruption time, with V IT recorded at 6.399 ms and C IT at 6.398 ms as illustrated in Fig. 11.Upon reclosing, CB 18 achieves a reclosing time of V RT 23.04 ms and C RT 27.01 ms as given in Fig. 12, indicating a shorter reclosing time compared to CB 9 .This is attributed to CB 18 's distance from the fault location compared to CB 9 , resulting in a quicker reclosing time.

Evaluation of the proposed system under diverse faults
The behaviour of the proposed adaptive protection strategy is investigated on a 13-bus system by applying multiple faults at different locations over a certain time period.Various fault scenarios of diverse nature (Diverse fault-F D ) are analysed to assess the robustness of the proposed strategy.A line-to-line fault lasting 5 s is  simulated at the radial connecting bus line L 5-9 , while a line-to-ground fault of the same duration is induced on lines L 6-7 and L CB-1 , linking the common bus and line L 1 .
Upon detection of the fault at L CB-1 , Kosaraju's algorithm identifies disengaged nodes and initiates Dial's algorithm to determine the shortest path from the fault location to the source DG.Relay R1, positioned nearest to the fault location and DG, is consequently activated to trip the circuit breaker CB 1 by sending a tripping signal.At the occurrence of the fault at L CB-1 , Kosaraju's algorithm analyses the situation and triggers the tripping of breaker CB 1 with an interruption time of V IT 6.399 ms and C IT of 6.398 ms.After fault clearance, the reclosing response time is recorded as V RT 23.04 ms and C RT 27.01 ms as mentioned Table 2.The results from the DSO depicted in Fig. 13 and the results shown in the Table 2, clarifies the proposed protection systems ability to interrupt the reverse fault current prompted by the DG connected near by the breakers location.
In Fig. 14 the breaker operation of CB 15 is depicted for the line-line fault occurred on the line L 5-9 under diverse fault conditions.For the fault occurred in L 5-9 the breakers CB 1 and CB 15 connected to the load, reacts by interrupting of the fault current.The interruption time V IT and C IT of CB 15 is 12.38 ms and 12.79 ms, followed by the reclosing time of V RT and C RT of 46.60 ms and 23.15 ms.Concurrently, breaker CB 7 , situated closer to the fault location L 6-7 , is tripped by relay R 7 at the same instant as CB 1 , with a fault interruption time of V IT 6.399 ms and C IT of 6.4 ms.The time taken for the breaker voltage and current to rise after reclosing is V RT 22.78 ms and C RT of 43.68 ms as depicted in Fig. 15.
Similarly, for the fault occurred on the radial connecting line L 5-9 circuit breaker CB 10 is tripped for the lineto-line fault, with the interruption time recorded as V IT 6.186 ms and C IT 6.398 ms.The reclosing time is noted as V RT 39.85 ms and C RT 35.77 ms as showed in Fig. 16.Instantaneous faults occurring at multiple locations are successfully interrupted and cleared within minimal time.All breakers in the 13-bus system reclose after fault    clearance with no peak in reclosing current, as evidenced by the real-time results.The reduced runtime of the proposed algorithm ensures faster fault detection and response, leading to improved system reliability, reduced downtime, and enhanced overall performance of the DC microgrid.The findings underscore the effectiveness of the proposed algorithm in promptly identifying and addressing faults, making it suitable for practical implementation in real-world scenarios.Its ability to detect simultaneous faults and react instantly to all fault types without delay is particularly advantageous for ensuring the stability and reliability of the DC microgrid system.By swiftly interrupting fault currents and initiating necessary corrective actions, the algorithm minimizes runtime, thereby enhancing the overall performance and efficiency of the microgrid system.

Conclusion
Incorporating adaptive techniques in existing z-source breaker topology is an emerging trend in DC microgrid protection.The GABPC aids in identifying the functional nodes that operate autonomously and swiftly deactivate the breaker in reaction to a fault.The DCCB verifies the proposed algorithm-based protection strategy in a 600 V/30 kW renewable integrated DC microgrid to validate the system under different fault conditions as given in Table 2 and in future MVDC and HVDC system will be considered.The function of bipartite matching helps to fix the relay threshold and the Kosaraju algorithm finds the functional and disengaged buses in transmission line.Thereby all the paths are noted from the location of the fault to the nearest operating distributed generation by Dial's algorithm.Henceforth, this amalgamation of proposed algorithm finds the least distance path from the fault location to the nearby distributed generation.This trips the bidirectional DC circuit breaker interfaced with proposed algorithm and provides the minimal time to detect and interrupt the Line to ground fault, line to line fault and diverse fault conditions.

Figure 3 .
Figure 3. (a) Voltage, current and power profile of DC microgrid system, (b).Breaker performance under step change in load condition.

Figure 4 .
Figure 4. Functionality of the proposed algorithm in DC microgrid.

Figure 5 .
Figure 5. 13-bus DC microgrid interfaced with Real time controller for Software in loop (SIL) testing.

Figure 7 . 8 Figure 8 .
Figure 7. Software in loop test results of CB 12 interrupting and reclosing during line-line fault.

Figure 9 .
Figure 9. Software in loop test results of CB 11 interrupting and reclosing during line-line fault.
14:14476 | https://doi.org/10.1038/s41598-024-65225-8www.nature.com/scientificreports/Evaluation of the proposed system under line-to-ground fault A Line-to-Ground fault (F G ) is simulated between lines L 8-9 for a duration of 5 s to verify the real-time performance of the proposed protection strategy.The circuit breakers positioned near the fault location trip following the relay signals initiated by the GABPC algorithm, activating relays R 9 , R 8 , R 10 , and R 18 to trip their corresponding breakers.The performance of CB 9 situated near the fault and CB 18 located nearby is compared in Figs.10, 11.

Figure 10 .
Figure 10.Software in loop test results of CB 9 interrupting and reclosing during line-ground fault.

Figure 11 .
Figure 11.Software in loop test results of CB 18 interrupting and reclosing during line-ground fault.

Figure 12 .
Figure 12.Software in loop test results of CB 1 interrupting and reclosing during diverse fault.

Figure 13 .Figure 14 .
Figure 13.Software in loop test results of CB 1 interrupting and reclosing during reverse fault current.

Figure 15 .
Figure 15.Software in loop test results of CB 7 interrupting and reclosing during diverse fault.

Figure 16 .
Figure 16.Software in loop test results of CB 10 interrupting and reclosing during diverse fault.

Table 1 .
Performance comparison of different fault detection algorithm under various conditions.

Table 2 .
Behaviour of the 13 bus system circuit breakers under different fault conditions.